First iteration of Alder Lake CPUs likely to have up-to 8 Big (P) Cores and 8 Little (E) Cores according to the Intel website, confirming earlier leaks.
A slide from Intel’s Architecture day, from which much has been inferred
Recent official communications from Intel have finally confirmed the processor core configurations we can expect to see on some of the upcoming 12th Generation Alder Lake CPUs. The info, revealed via the Intel Game Dev developer partnership microsite, specifies typical core configurations for mobile-class and desktop-class processors alongside broader optimisations recommended for software developed for the new platform.
First, a little bit of terminology. Alder Lake utilises what’s known as a big.LITTLE architecture design with two specific types of CPU core: the P or Performance type, and E or Efficiency type. P-Cores are bigger, operate at higher frequencies, support hyperthreading and are designed for intensive tasks. E-Cores by contrast are more efficient, single-threaded, and optimised for background tasks or operating as a pool of resources to be tapped into opportunistically (for example, when the task requires a little more processing power than offered by the P-Cores alone). Each P-Core has its own L1 and L2 cache pools, groups of four E-Cores share L2 cache, and a large L3 cache is shared across the processor as a whole.
The architectural codenames for P-Cores and E-Cores are Golden Cove and Gracemont respectively; they’re direct successors to Willow Cove (as seen on Tiger Lake) and Tremont core microarchitectures, the latter of which being key to Intel’s recent ultra-low power processor designs. Although it was initially stated that AVX-512 instructions would be supported, Intel later clarified that this crop of Alder Lake processors will not support AVX-512 in any configuration.
Intel’s Desktop Alder Lake processors will have up to 8 P-Cores and 8 E-Cores, supporting 24 independent threads in total. The base configuration however will only have 6 P-Cores and no E-Cores, supporting only 12 independent threads thanks to hyperthreading. Given the audience, this base should be an ‘entry level gaming’ chip in the Core i5-x400 class rather than the true entrypoint into the ADL ecosystem.
Mobile Alder Lake chips are a much more diverse affair. They feature up to 6 P-Cores and 8 E-Cores, but the base model is a 2 P-Core / 8 E-Core design; this mismatch between desktop and mobile could be a significant headache for developers, but it’s worth noting that each SKU detailed to this point supports at least 12 computation threads. The range also features 96 GPU Execution Units, far more than the 32 of the desktop models.
This information obliquely defines the processors hinted at during the Intel Architecture Day in August. Using them as a reference at the time was logical but open to misinterpretation, today we can be much more confident of their existence.
To take advantage of the big.LITTLE approach both OS schedulers and software will need to be aware of the cores, aware of their differences, and able to discern or specify which is better for a particular task or group of tasks. That’s an additional aspect of architectural awareness than had been required in the past, and something that middleware in particular will need to exploit sooner rather than later.
It’s looking increasingly likely that more will be revealed by Intel before the end of the month, potentially coinciding with the Intel ON Innovation digital event next week. The additional complexities of the platform will mean that discussions over the various pros and cons of each platform will continue well into 2022.
SOURCE: Intel.com, Tweakers.net
