JEDEC announces the publication of JESD209-5, also known as the Low Power Double Data Rate 5 (LPDDR5) standard, which features specifications with an I/O rate of 6400MT/s.
JEDEC announces the publication of JESD209-5, also known as the Low Power Double Data Rate 5 (LPDDR5) standard, which features specifications with an I/O rate of 6400MT/s.
Press Release
JEDEC announces the publication of JESD209-5, also known as the Low Power Double Data Rate 5 (LPDDR5) standard, which features specifications with an I/O rate of 6400MT/s. With this, LPDDR5 is expected to be 50% higher than the first version of LPDDR4. The updated LPDDR5 specifications will deliver a significant boost of memory speed and efficiency is a wide variety of applications including mobile devices, notebooks, ultrabooks, and others. LPDDR5 device density ranges from 2GB to 32 GB. With that, we could expect the LPDDR5 standard kits for gaming notebooks to come in 64GB (2x32GB) DDR5-6400 kits. Samsung first introduced its 8GB LPDDR5 memory in July 2018, LPDDR5 and DDR5 are expected to arrive this year and to be used in next-generation devices.
LPDDR5 features double the memory throughput of the previous standard, LPDDR4. LPDDR5 will have a data rate of 6400MT/s compared to 3200MT/s for LPDDR4 as released in 2014. LPDDR5 will have an enormous impact on the performance and capabilities of the next-generation portable computing devices. To achieve this performance improvement, LPDDR5 architecture was redesigned; moving to 16Banks programmable architecture and multi-clocking architecture.
LPDDR5 features two new command-based operations to achieve higher data transmission and better power consumption: Data-Copy and Write-X. The Data-Copy command instructs the LPDDR5 device to copy data transmitted on a single I/O pin to the other I/O pins, eliminating the need to transmit data to the other pins. The Write-X command instructs the device to write all-ones or all-zeros to a specific address, eliminating the need to send data from the SoC to the LPDDR5 device. Reducing data transmission with these new commands will help reduce overall system power consumption. LPDDR5 also introduces the support of Link Error Correcting Code (ECC) on the interface between the SoC and DRAM.
JESD209-5 is available for download at the JEDEC website.
