Faulty transistor in 3Gbps PLL clocking tree
Faulty transistor in 3Gbps PLL clocking tree
Yesterday Vortez reported on the design flaw with Intel’s 6-series chipset, part of the new Sandy Bridge platform. Today, thanks to Anandtech, we have further clarification on the exact source of the reported issues.
The problem arises from a faulty transistor in the SATA 3Gbps PLL clocking tree, which leaks current, subsequently causing a failure of the SATA ports 2-5. SATA ports 0-1 are unaffected as they use a different, 6 Gbps PLL clocking tree.
Intel’s solution is to simply cut off voltage to the problematic transistor, and as it is not an essential part of the chipset design, there is no loss of functionality. There have been several redesigns of the chipset throughout the development cycle of Cougar Point, and it seems as though this transistor is a remnant of those. The problem only occurs in the B-stepping of the chipset, which is the one that was shipped to customers. Intel cite the problem as being a ‘simple oversight’, albeit a costly one.
Around 8 million Sandy Bridge chipsets have been shipped since the release at CES in January, and with a budget of $700m for Intel to rectify the issue, this works out at $87.50 per chipset, almost the cost of an entire motherboard.
However, Intel also stress in the article that the recall does not necessarily affect all chipsets. For example, many notebook motherboard designs will not use SATA ports 2-5 and thus will be unaffected by the issue.
The best advice for now is to try to avoid the 3Gbps SATA ports on effected motherboards, and simply use ports 0-1 if possible. Expect more news from Vortez on this issue as it comes. Discuss these developments in the forums.
Source: Anandtech
