Double the bandwidth is the obvious headline, but eyes will be drawn to the potential for supplying 300+ Watts of power over an x16 slot.
Double the bandwidth is the obvious headline, but eyes will be drawn to the potential for supplying 300+ Watts of power over an x16 slot.
PCI-Express 3.0 has been in use in the desktop PC platform for nigh on the past five years, offering a doubling of bandwidth per lane vs PCI-E 2.0 and a modification of the line code from 8b/10b to the more efficient 128b/130b system in use today. Even in that time the spec has rarely been pushed to its full potential by peripheral hardware, and only in specific (and rare) configurations have GPUs and more recently high-speed storage stretched the almost 1 Gigabyte per second per lane (bidirectionally) potential of the interface. However computing is a voracious beast eager for higher speed and new developments, and I/O standards are no different to any other aspect of the industry.
Version 0.7 of PCI-Express 4.0’s draft specification may be ready as soon as the end of the month and PCI-SIG, the steering committee responsible for its development, have shared some of its features ahead of time. Touching on maximum rate of transfers per second, bandwidth and power delivery, the specs thus far are another step function above the capabilities of today.
As with the transition from PCI-E 2.0 to 3.0 the latest specification demands yet another doubling of bandwidth, this time from 984MB/s to a monumental 1.969 GB/s per-lane, per-direction – finally breaching the 1GB/s barrier. Unlike PCI-E 3.0 however the encoding standard isn’t changing, so this boost in performance is down to a raw doubling the data transfer rate – from 8 to 16 GT/s (billion transfers per second). As a result the maximum available (theoretical) bandwidth on an x16 PCI-E 4.0 slot is a shade under 32GB/s compared with close to 16GB/s today.
A simple increase in bandwidth for PCI-E 4.0 is unlikely to prove disruptive to the desktop platform as a whole, but the same cannot be said for increases in supplied power. Currently the PCI-E 3.0 specification determines a maximum power of 75W per slot, derived from a combination of 3.3V and 12V lines; PCI-E 4.0 would be able to provide as much as 300W, or perhaps even more depending on the final proposals for the standard. That’s enough to supply a high performance GPU without the need for auxiliary PCI-E power connectors on the card itself, potentially cleaning up the interior of the PC considerably as well as unlocking the potential for new card form factors.
Of course, the standard desktop PC motherboard isn’t equipped for supplying 300+ Watts over a PCI-E slot, nor are most GPUs capable of drawing that much power directly through the slot. The first PCI-E 4.0 motherboards may even make use of 6/8-pin PCI-E power connectors on the motherboard itself, similar to current premium designs that support 3/4-way multi-GPU configurations. A more universal switch, if and when it comes, will be significant to both markets; in the short term however the benefits are likely to be realised only in the enterprise computing sector, particularly datacentres and supercomputing.
Finally, PCI-SIG are also proposing a new PCI-Express-Over-Cable solution tentatively named OCuLink, a contraction of Optical/Copper Link. Described as ‘PCIe Outside The Box’, this standard leverages PCI-E 4.0 signalling through a cable suitable for both internal and external use cases that would allow you to hook up high-speed components such as SSD storage and even GPUs. Starting at 8GT/s, OCuLink would offer up to 32Gbps bandwidth in the first iteration; USB 3.1 by contrast currently offers 5Gbps bidirectionally. It could in theory replace the still nascent U.2 internal connector in the medium term, depending on cost. Although a partial competitor to Intel’s Thunderbolt I/O, OCuLink wouldn’t offer native USB 3.1 and Displayport support and so could be seen as less desirable due to a lack of flexibility.
Far more detail on PCI-Express 4.0 can be found over at Tom’s Hardware, who had a sit-down discussion at the Intel Developer Forum with PCI-SIG VP Richard Solomon. If you’re interested in much of the minutia we urge you to give it a read.
