CPU and APU speaks leaked, giving extended detail into Zen architecture.
CPU and APU speaks leaked, giving extended detail into Zen architecture.
In an IT technical forum discussion, a CERN AMD Zen would arrive at some point in a 32-core CPU. A slide from the engineers presentation also proclaims that Zen will have a 40% improvement in instructions per clock (IPC) and that it will also launch with a Symmetrical Multi-threading (SMT) design.
The 32 core Zen part is believed to be a server part. You can read an article about the leaked 32 core Zen part here. AMD also plans to release an APU along with the 32 core part.The APU is designed with a die-optimized version of Polaris GPU integrated onto the CPU packaging. This APU comes with a 2000 core Polaris GPU provided on die and a 16 core Zen CPU.
The Zen will have a 576-Bit memory controller that utilizes up to 3200MHz DDR4 at 204.8 GB/s. This part will also utilize a 64MB L3 cache. The Zen APU will have a 288-Bit memory controller that uses DDR4 3200MHz with a bandwidth of 102.4 Gb/s and no L3 cache. But the APU will utilize a 2000 core polaris GPU with 8GB of HBM2 memory with a bandwidth of 512 GB/s with a 2048-bit memory controller. Full specs will be listed below.
AMD Zen High End ‘Exascale’ CPU, 1-4 Socket (1P-4P) – Specs As Per CERN
-32 ZEN x86 Core, 6-wide
-12 8KB L0 Cache (4KB per core)
-2 MB L1 D-Cache (64KB per core)
-2 MB L1 I-Cache (64 KB per core)
-16 MB L2 Cache (512 KB per core)
-64? MB L3 Cache (8MB cluster per quad unit)
-576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
-204.8 GB/s via DDR4-3200 (ECC Off)
-170.6 GB/s via DDR4-2666 (ECC On)
AMD Zen High End Exascale APU, 1-2 Socket (1P-2P) – Specs From Fast Forwar
-16 ZEN x86 Core, 6-wide
-64 KB L0 Cache (4KB per core)
-1 MB L1 D-Cache (64KB per core)
-1 MB L1 I-Cache (64 KB per core)
-8 MB L2 Cache (512 KB per core)
-No L3 Cache
-288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
-102.4 GB/s via DDR4-3200 (ECC Off)
-85.3 GB/s via DDR4-2666 (ECC On)
-102.4 GB/s between CPU and GPU via GMI
-~2000-core Polaris GPU
-2048-bit GPU Memory Controller
-8 GB HBM2 SGRAM Memory (2 chips at 4GB)
-512 GB/s GPU Bandwidth
-32 ZEN x86 Core, 6-wide
-12 8KB L0 Cache (4KB per core)
-2 MB L1 D-Cache (64KB per core)
-2 MB L1 I-Cache (64 KB per core)
-16 MB L2 Cache (512 KB per core)
-64? MB L3 Cache (8MB cluster per quad unit)
-576-bit Memory Controller (8×72-bit, 64-bit + 8-bit ECC)
-204.8 GB/s via DDR4-3200 (ECC Off)
-170.6 GB/s via DDR4-2666 (ECC On)
AMD Zen High End Exascale APU, 1-2 Socket (1P-2P) – Specs From Fast Forwar
-16 ZEN x86 Core, 6-wide
-64 KB L0 Cache (4KB per core)
-1 MB L1 D-Cache (64KB per core)
-1 MB L1 I-Cache (64 KB per core)
-8 MB L2 Cache (512 KB per core)
-No L3 Cache
-288-bit CPU Memory Controller (4×72-bit, 64-bit + 8-bit ECC)
-102.4 GB/s via DDR4-3200 (ECC Off)
-85.3 GB/s via DDR4-2666 (ECC On)
-102.4 GB/s between CPU and GPU via GMI
-~2000-core Polaris GPU
-2048-bit GPU Memory Controller
-8 GB HBM2 SGRAM Memory (2 chips at 4GB)
-512 GB/s GPU Bandwidth
SOURCE: VR World
